4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ERASE SEQUENCE
ERASE SUSPENSION
Executing an ERASE sequence sets all bits within a
block to logic 1. The command sequence necessary to
executeanERASEissimilartothatofaWRITE. Toprovide
addedsecurityagainstaccidentalblockerasure, twocon-
secutivecommandcyclesarerequiredtoinitiateanERASE
of a block. In the first cycle, addresses are “Don’t Care,”
and ERASE SETUP (20h) is given. In the second cycle, VPP
must be brought to VPPH, an address within the block to
be erased must be issued, and ERASE CONFIRM (D0h)
must be given. If a command other than ERASE CON-
FIRM is given, the write and erase status bits (SR4 and
SR5) are set, and the device is in the status register read
mode.
TheonlycommandthatmaybeissuedwhileanERASE
is in progress is ERASE SUSPEND. This command en-
ables other commands to be executed while pausing the
ERASE in progress. When the device has reached the
erase suspend mode, the erase suspend status bit (SR6)
and ISM status bit (SR7) are set. The device may now be
given a READ ARRAY, ERASE RESUME or READ STATUS
REGISTER command. After READ ARRAY has been is-
sued, any location not within the block being erased may
be read. If ERASE RESUME is issued before SR6 has been
set, the device immediately proceeds with the ERASE in
progress.
After the ERASE CONFIRM (D0h) is issued, the ISM
starts the ERASE of the addressed block. Any READ op-
eration outputs the status register contents on DQ0–
DQ7. VPP must be held at VPPH until the ERASE is com-
pleted (SR7 = 1). When the ERASE is completed, the
device is in the status register read mode until another
command is issued. Erasing the boot block also requires
that either the RP# pin be set to VHH or the WP# pin be
held HIGH at the same time VPP is set to VPPH.
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits has
been set, an error has occurred. The ISM cannot reset
these three bits. To clear these bits, CLEAR STATUS REG-
ISTER (50h) must be given. If the VPP status bit (SR3) is set,
further WRITE or ERASE operations cannot resume until
the status register is cleared. Table 4 lists the combina-
tion of errors.
Table 4
Status Register Error Code Description
1
STATUS BITS
SR4
SR5
0
SR3
0
ERROR DESCRIPTION
0
0
1
1
0
0
1
1
No errors
0
1
VPP voltage error
0
0
WRITE error
0
1
WRITE error, VPP voltage not valid at time of WRITE
ERASE error
1
0
1
1
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
Command sequencing error or WRITE/ERASE error
1
0
1
1
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.
4MbSmart3BootBlockFlashMemory
F45_3.p65 – Rev. 3, Pub. 12/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
13
MICRON [ MICRON TECHNOLOGY ]
