4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
POWER-UP
The MT28F004B3 and MT28F400B3 are designed and
fabricated to meet advanced firmware storage require-
ments. To ensure this level of reliability, VPP must be at
3.3V ±0.3V or 5V ±10% during WRITE or ERASE cycles.
Due to process technology advances, 5V VPP is optimal
for application and production programming.
The likelihood of unwanted WRITE or ERASE opera-
tions is minimized because two consecutive cycles are
required to execute either operation. However, to reset
the ISM and to provide additional protection while VCC is
ramping, one of the following conditions must be met:
•
RP# must be held LOW until VCC is at valid
functional level; or
•
CE# or WE# may be held HIGH and
RP# must be toggled from VCC-GND-VCC.
POWER USAGE
The MT28F004B3 and MT28F400B3 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down mode
is enabled by bringing RP# LOW. Current draw (ICC) in
this mode is a maximum of 8µA at 3.3V VCC. When CE# is
HIGH, the device enters standby mode. In this mode,
maximum ICC current is 100µA at 3.3V VCC. If CE# is
broughtHIGHduringaWRITEorERASE, theISMcontin-
ues to operate, and the device consumes the respective
active power until the WRITE or ERASE is completed.
After a power-up or RESET, the status register is reset,
and the device enters the array read mode.
RP#
Note 1
V
CC
(3.3V)
t
AA
Address
VALID
VALID
Data
t
RWH
UNDEFINED
NOTE: 1. VCC must be within the valid operating range before RP#
goes HIGH.
Figure 2
Power-Up/Reset Timing Diagram
4MbSmart3BootBlockFlashMemory
F45_3.p65 – Rev. 3, Pub. 12/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
14
MICRON [ MICRON TECHNOLOGY ]
