256Mb, 3V Multiple I/O Serial Flash Memory
XIP Mode
Confirmation Bit Settings Required to Activate or Terminate XIP
The XIP confirmation bit setting activates or terminates XIP after it has been enabled or
disabled. This bit is the value on DQ0 during the first dummy clock cycle in the FAST
READ operation. In dual I/O XIP mode, the value of DQ1 during the first dummy clock
cycle after the addresses is always "Don't Care." In quad I/O XIP mode, the values of
DQ3, DQ2, and DQ1 during the first dummy clock cycle after the addresses are always
"Don't Care."
Table 39: XIP Confirmation Bit
Bit Value
Description
0
1
Activates XIP: While this bit is 0, XIP remains activated.
Terminates XIP: When this bit is set to 1, XIP is terminated and the device returns to SPI.
Table 40: Effects of Running XIP in Different Protocols
Protocol
Effect
Extended I/O
and Dual I/O
In a device with a dedicated part number where RESET# is enabled, a LOW pulse on that pin re-
sets XIP and the device to the state it was in previous to the last power-up, as defined by the
nonvolatile configuration register.
Dual I/O
Values of DQ1 during the first dummy clock cycle are "Don't Care."
Quad I/O1
Values of DQ[3:1] during the first dummy clock cycle are "Don't Care." In a device with a dedica-
ted part number, it is only possible to reset memory when the device is deselected.
1. In a device with a dedicated part number where RESET# is enabled, a LOW pulse on that
pin resets XIP and the device to the state it was in previous to the last power-up, as de-
fined by the nonvolatile configuration register only when the device is deselected.
Note:
Terminating XIP After a Controller and Memory Reset
The system controller and the device can become out of synchronization if, during the
life of the application, the system controller is reset without the device being reset. In
such a case, the controller can reset the memory to power-on reset if the memory has
reset functionality. (Reset is available in devices with a dedicated part number.)
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)
These sequences cause the controller to set the XIP confirmation bit to 1, thereby termi-
nating XIP. However, it does not reset the device or interrupt PROGRAM/ERASE opera-
tions that may be in progress. After terminating XIP, the controller must execute RESET
ENABLE and RESET MEMORY to implement a software reset and reset the device.
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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