256Mb, 3V Multiple I/O Serial Flash Memory
Initial Delivery Status
Power Loss Recovery
For power loss recovery, the second part of the sequence is exiting from dual- or quad-
SPI protocol by using the following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock
cycles within S# LOW; S# becomes HIGH before 9th clock cycle. After this two-part se-
quence the extended-SPI protocol is active.
Interface Rescue
For interface rescue, the second part of the sequence is for exiting from dual or quad-
SPI protocol by using the following FFh sequence: DQ0 and DQ3 equal to 1 for 16 clock
cycles within S# LOW; S# becomes HIGH before 17th clock cycle. For DTR protocol, 1
should be driven on both edges of clock for 16 cycles with S# LOW. After this two-part
sequence, the extended-SPI protocol is active.
Initial Delivery Status
The device is delivered as follows:
• Memory array erased: all bits are set to 1 (each byte contains FFh)
• Status register contains 00h (all status register bits are 0)
• Nonvolatile configuration register (NVCR) bits all erased (FFFFh)
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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