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MT250QL01GCBA1ESE0SATES 参数 Datasheet PDF下载

MT250QL01GCBA1ESE0SATES图片预览
型号: MT250QL01GCBA1ESE0SATES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
4-BYTE READ MEMORY Operations  
4-BYTE READ MEMORY Operations  
Table 23: 4-BYTE READ MEMORY Operations  
Operation Name  
Description/Conditions  
4-BYTE READ (13h)  
READ MEMORY operations can be extended to a 4-byte address range,  
with [A31:0] input during address cycle.  
4-BYTE FAST READ (0Ch)  
Selection of the 3-byte or 4-byte address range can be enabled in two  
ways: through the nonvolatile configuration register or through the ENA-  
BLE 4-BYTE ADDRESS MODE/EXIT 4-BYTE ADDRESS MODE commands.  
Each address bit is latched in during the rising edge of the clock. The ad-  
dressed byte can be at any location, and the address automatically incre-  
ments to the next address after each byte of data is shifted out; there-  
fore, a die can be read with a single command.  
4-BYTE DUAL OUTPUT FAST READ (3Ch)  
4-BYTE DUAL INPUT/OUTPUT FAST READ (BCh)  
4-BYTE QUAD OUTPUT FAST READ (6Ch)  
4-BYTE QUAD INPUT/OUTPUT FAST READ  
(ECh)  
DTR 4-BYTE FAST READ (0Eh)  
FAST READ can operate at a higher frequency (fC).  
DTR 4-BYTE DUAL INPUT/OUTPUT FAST READ  
(BEh)  
4-BYTE commands and DTR 4-BYTE commands function in 4-BYTE and  
DTR 4-BYTE protocols regardless of settings in the nonvolatile configura-  
DTR 4-BYTE QUAD INPUT/OUTPUT FAST READ tion register or enhanced volatile configuration register; other commands  
(EEh)  
function in 4-BYTE and DTR protocols only after the specific protocol is  
enabled by the register settings.  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
49  
© 2014 Micron Technology, Inc. All rights reserved.  
 
 
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