512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Mode Register Definition
Table 5:
Burst Definition Table
Order of Accesses Within a Burst
Starting Column
Burst Length
Address
Type = Sequential
Type = Interleaved
A0
0
2
0-1
1-0
0-1
1-0
1
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
8
0
1
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Notes: 1. For a burst length of two, A1–Ai select the two-data-element block; A0 selects the first
access within the block.
2. For a burst length of four, A2–Ai select the four-data-element block; A0–A1 select the first
access within the block.
3. For a burst length of eight, A3–Ai select the eight-data-element block; A0–A2 select the
first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
5. i = 9 for 512MB
i = 9, 11 for 1GB
Table 6:
CAS Latency Table
Allowable Operating Clock Frequency (MHz)
Speed
CL = 2
CL = 2.5
-335
-262
-26A
-265
-202
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
75 ≤ f ≤ 100
75 ≤ f ≤ 166
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 125
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
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