512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
General Description
General Description
The MT18VDVF6472D and MT18VDVF12872D are high-speed CMOS, dynamic random-
access, 512MB and 1GB memory modules organized in x72 (ECC) configuration. DDR
SDRAM modules use internally configured quad-bank DDR SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. Double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the device bank and row to be accessed (BA0,
BA1 select devices bank; A0–A12 select device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the device bank and starting
device column location for the burst access.
DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4,
or 8 locations. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and acti-
vation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II compatible. For more information regarding DDR SDRAM operation, refer to the
256Mb or 512Mb DDR SDRAM component data sheets.
PLL and Register Operation
DDR SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR SDRAM devices. The registers and PLL minimize system and clock
loading.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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