512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Mode Register Definition
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2 or 2.5
clocks, as shown in Figure 5, "CAS Latency Diagram," on page 14.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Figure 6, "CAS Latency
Table," on page 13, indicates the operating frequencies at which each CAS latency set-
ting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 4:
Mode Register Definition Diagram
BA1
A8
A6 A5 A4
A1
A0
Address Bus
BA0
A10
A7
A3 A2
A12 A11
A9
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
M3 = 0
Reserved
2
M3 = 1
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Reserved
M12 M11 M10 M9 M8 M7
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
0
0
-
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
Normal Operation/Reset DLL
All other states reserved
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
12
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