欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT18VDDT3272AY-40B 参数 Datasheet PDF下载

MT18VDDT3272AY-40B图片预览
型号: MT18VDDT3272AY-40B
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR SDRAM UNBUFFERED DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 29 页 / 679 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第21页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第22页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第23页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第24页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第25页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第26页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第28页浏览型号MT18VDDT3272AY-40B的Datasheet PDF文件第29页  
256MB, 512MB, 1GB (x72, ECC, DR), PC3200  
184-PIN DDR SDRAM UDIMM  
Ta b le 21: Se ria l Pre se n ce -De t e ct Ma t rix  
“1”/0”: Serial Data, “driven to HIGH/driven to LOW”  
BYTE  
DESCRIPTION  
ENTRY (VERSION) MT18VDDT3272A MT18VDDT6472A MT18VDDT12872A  
0
1
2
3
128  
256  
80  
08  
07  
0C  
80  
08  
07  
0D  
80  
08  
07  
0D  
Number of SPD Bytes Used by Micron  
Total Number of Bytes in SPD Device  
Fundamental Memory Type  
Number of Row Addresses on  
Assembly  
SDRAM DDR  
12, 13  
4
Number of Column Addresses on  
Assembly  
10, 11  
0A  
0A  
0B  
5
6
7
8
9
2
72  
0
02  
48  
00  
04  
50  
02  
48  
00  
04  
50  
02  
48  
00  
04  
50  
Number of Physical Ranks on DIMM  
Module Data Width  
Module Data Width (Continued)  
Module Voltage Interface Levels  
SDRAM Cycle Time, tCK  
CAS Latency = 3  
SSTL 2.5V  
5ns (-40B)  
t
10  
0.7ns (-40B)  
70  
70  
70  
SDRAM Access from Clock, AC  
CAS Latency = 3  
11  
12  
ECC  
02  
80  
08  
02  
82  
08  
02  
82  
08  
Module Configuration Type  
Refresh Rate/Type  
15.62µs, 7.8µs/SELF  
8
13 SDRAM Device Width (Primary DDR  
SDRAM)  
14  
8
08  
01  
08  
01  
08  
01  
Error-checking DDR SDRAM Data  
Width  
15  
1 clock  
Minimum Clock Delay, Back-to-Back  
Random Column Access  
16 Burst Lengths Supported  
2, 4, 8  
4
0E  
04  
0E  
04  
0E  
04  
17  
Number of Banks on DDR SDRAM  
Device  
18 CAS Latencies Supported  
3, 2.5, 2  
0
1C  
01  
02  
20  
1C  
01  
02  
20  
1C  
01  
02  
20  
19  
20  
CS Latency  
WE Latency  
1
21 SDRAM Module Attributes  
Unbuffered/Diff.  
Clock  
22  
23  
Fast/Concurrent AP  
6ns (for PC2700  
system compatibility)  
C0  
60  
C0  
60  
C0  
60  
SDRAM Device Attributes: General  
SDRAM Cycle Time, tCK  
(CAS Latency = 2.5)  
t
24  
25  
0.7ns (for PC 2700  
system compatibility)  
70  
75  
70  
75  
70  
75  
SDRAM Access from CK, AC  
(CAS Latency = 2.5)  
SDRAM Cycle Time, tCK  
(CAS Latency = 2)  
7.5ns (for PC 2100  
and PC 1600 system  
compatibility)  
t
26  
0.75ns (for PC 2100  
and PC 1600 system  
compatibility)  
75  
75  
75  
SDRAM Access from CK, AC  
(CAS LATENCY = 2)  
t
27  
28  
15ns (-40B)  
3C  
28  
3C  
28  
3C  
28  
Minimum Row Precharge Time, RP  
10ns (-40B)  
Minimum Row Active to Row Active,  
tRRD  
t
29  
30  
15ns (-40B)  
40ns (-40B)  
3C  
28  
3C  
28  
3C  
28  
Minimum RAS# to CAS# Delay, RCD  
t
Minimum RAS# Pulse Width, RAS  
pdf: 09005aef80814e61, source: 09005aef80a43eed  
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2004 Micron Technology, Inc.  
27  
 复制成功!