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MT16VDDT12864AG-262 参数 Datasheet PDF下载

MT16VDDT12864AG-262图片预览
型号: MT16VDDT12864AG-262
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR SDRAM UNBUFFERED DIMM]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 35 页 / 875 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256MB, 512MB, 1GB, 2GB (x64, DR)  
184-PIN DDR SDRAM UDIMM  
Ta b le 22: Se ria l Pre se n ce -De t e ct Ma t rix (256MB, 512MB, a n d 1GB)  
“1”/0”: Serial Data, “driven to HIGH/driven to LOW”; notes appear on page 31  
BYTE  
DESCRIPTION  
ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A  
0
1
2
3
128  
256  
80  
08  
07  
0C  
80  
08  
07  
0D  
80  
08  
07  
0D  
Number of SPD Bytes Used by Micron  
Total Number of Bytes in SPD Device  
Fundamental Memory Type  
SDRAM DDR  
12, 13  
Number of Row Addresses on  
Assembly  
4
10, 11  
0A  
0A  
0B  
Number of Column Addresses on  
Assembly  
5
6
7
8
9
Number of Physical Ranks on DIMM  
Module Data Width  
2
02  
40  
00  
04  
2
2
64  
0
40  
00  
04  
40  
00  
04  
Module Data Width (Continued)  
Module Voltage Interface Levels  
SDRAM Cycle Time, tCK, (CAS Latency  
= 2.5) (See note 1)  
SSTL 2.5V  
6ns (-335)  
7ns (-262/-26A)  
7.5ns (-265)  
60  
70  
75  
60  
70  
75  
60  
70  
75  
t
10  
0.7ns (-335)  
0.75ns (-262/-26A/-265)  
70  
75  
70  
75  
70  
75  
SDRAM Access From Clock, AC  
(CAS Latency = 2.5)  
11  
12  
13  
None  
00  
80  
08  
00  
82  
08  
00  
82  
08  
Module Configuration Type  
Refresh Rate/Type  
15.62µs, 7.8µs/SELF  
8
SDRAM Device Width (Primary DDR  
SDRAM)  
14  
15  
Error-Checking DDR SDRAM Data Width  
None  
00  
01  
00  
01  
00  
01  
Minimum Clock Delay, Back-to-Back  
Random Column Access  
1 clock  
16  
17  
18  
19  
20  
21  
2, 4, 8  
0E  
04  
0C  
01  
02  
20  
0E  
04  
0C  
01  
02  
20  
0E  
04  
0C  
01  
02  
20  
Burst Lengths Supported  
Number of Banks on DDR SDRAM Device  
CAS Latencies Supported  
CS Latency  
4
2, 2.5  
0
1
WE Latency  
Unbuffered/Diff.  
Clock  
SDRAM Module Attributes  
22  
23  
Fast/Concurrent AP  
C0  
C0  
C0  
SDRAM Device Attributes: General  
SDRAM Cycle Time, tCK  
(CAS Latency = 2)  
7.5ns (-335/-262/-26A)  
10ns (-265  
75  
A0  
75  
A0  
75  
A0  
SDRAM Access From CK, tAC  
(CAS Latency = 2)  
SDRAM Cycle Time, tCK  
(CAS Latency = 1.5)  
SDRAM Access From CK, tAC  
(CAS Latency = 1.5)  
24  
25  
26  
27  
0.7ns (-335)  
0.75ns (-262/-26A/-265)  
70  
75  
70  
75  
70  
75  
N/A  
00  
00  
00  
N/A  
00  
00  
00  
t
18ns (-335)  
15ns (-262)  
20ns (-26A/-265)  
48  
3C  
50  
48  
3C  
50  
48  
3C  
50  
Minimum Row Precharge Time, RP  
(see note 4)  
pdf: 09005aef80739fa5, source: 09005aef807397e5  
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2004 Micron Technology, Inc.  
29  
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