256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
SPD Clo ck a n d Da t a Co n ve n t io n s
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 13, Data Validity, and Figure 14, Defi-
nition of Start and Stop).
SPD Ackn o w le d g e
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either m aster or slave, will release the bus after trans-
m itting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 15, Acknowledge Response From Receiver).
SPD St a rt Co n d it io n
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
m onitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the m aster, the slave will continue to transm it data. If
an acknowledge is not detected, the slave will termi-
nate further data transm issions and await the stop
condition to return to standby power m ode.
All com m ands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
m et.
SPD St o p Co n d it io n
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Fig u re 13: Da t a Va lid it y
Fig u re 14: De fin it io n o f St a rt a n d St o p
SCL
SCL
SDA
SDA
DATA STABLE
DATA
DATA STABLE
CHANGE
START
BIT
STOP
BIT
Fig u re 15: Ackn o w le d g e Re sp o n se Fro m Re ce ive r
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
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©2004 Micron Technology, Inc.
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