256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Ta b le 23: Se ria l Pre se n ce -De t e ct Ma t rix (2GB) (Co n t in u e d )
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDT25664A
Address and Command Hold Time, tIH, (See note 2)
33
0.8ns (-335)
1.0ns (-262/-26A/-265)
80
A0
Data/Data Mask Input Setup Time, tDS
34
35
0.45ns (-335)
0.5ns (-262/-26A/-265)
45
50
Data/Data Mask Input Hold Time, tDH
0.45ns (-335)
0.5ns (-262/-26A/-265)
45
50
36-40
41
00
Reserved
t
60ns (-335/-262)
65ns (-26A/-265)
3C
41
Min Active Auto Refresh Time RC
42
120ns (all speed grades)
78
Minimum Auto Refresh to Active/ Auto Refresh
Command Period, tRFC
t
43
44
45
12ns (-335)
13ns (-262/-26A/-265)
30
34
SDRAM Device Max Cycle Time CKMAX
t
0.45ns (-335)
0.5ns (-262/-26A/-265)
2D
32
SDRAM Device Max DQS-DQ Skew Time DQSQ
0.55ns (-335)
0.75ns (-262/-26A/-265)
55
75
SDRAM Device Max Read Data Hold Skew Factor
tQHS
46-61 Reserved
00
01/11
00
47
DIMM Height
Standard/Low-Profile
Release 1.0
46-61 Reserved
62
63
SPD Revision
10
Checksum For Bytes 0-62
-335
-262
-26A
-265
1B/2B
AB/BB
D8/E8
1C/2C
64
65-71
72
MICRON
(Continued)
01–12
2C
FF
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code
Manufacturing Location
01–0C
73-90
91
Variable Data
Variable Data
00
Module Part Number (ASCII)
PCB Identification Code
92
0
Identification Code (Continued)
Year of Manufacture in BCD
Week of Manufacture in BCD
Module Serial Number
93
Variable Data
Variable Data
Variable Data
–
94
95-98
99-127
Manufacturer-specific Data (RSVD)
NOTE:
1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.
t
t
2. The value of RAS used for -26A/-265 modules is calculated from RC - tRP. Actual device spec. value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
t
t
4. The value of RP, tRCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR
SDRAM device specification is 15ns.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
33
MICRON [ MICRON TECHNOLOGY ]
