512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 17: EEPROM Device Select Code
Most significant bit (b7) is sent first.
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
B0
SELECT CODE
b7
b6
b5
b4
b3
b2
b1
Memory Area Select Code (two arrays)
Protection Register Select Code
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Table 18: EEPROM Operating Modes
MODE
RW BIT
WC
BYTES INITIAL SEQUENCE
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current Address Read
Random Address Read
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
1
O 1
1
Sequential Read
Byte Write
VIL
? 16
Page Write
START, Device Select, RW = ‘0’
Figure 14: SPD EEPROM Timing Diagram
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
UNDEFINED
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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