512MB, 1GB (x64)
200-PIN DDR SODIMM
ple of tCK that meets the maximum absolute
value for tRAS.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC)
or VIH(DC).
22. The valid data window is derived by achieving
26. JEDEC specifies CK and CK# input slew rate must
be O 1V/ns (2V/ns differentially).
other specifications: tHP (tCK/2), tDQSQ, and tQH
(tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 8, Derating
Data Valid Window, shows derating curves for
duty cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
t
must be derated: 50ps must be added to DS and
tDH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. VDD must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
Figure 8: Derating Data Valid Window
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
3.750
3.700
3.650
3.600
3.550
3.400
3.500
3.450
3.350
3.300
3.400
3.350
3.300
3.250
3.200
3.150
3.250
3.100
3.050
NA -335
3.000
2.950
t
-262/-26A/-265 @ CK = 10ns
-202 @ CK = 10ns
-262/-26A/-265 @ CK = 7.5ns
-202 @ CK = 8ns
2.900
t
t
t
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
21
MICRON [ MICRON TECHNOLOGY ]
