512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Table 15: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 19
Byte
Description
Entry (Version) MT16HTF6464A MT16HTF12864A MT16HTF25664A
MIN row active to row active, tRRD
MIN RAS#-to-CAS# delay, tRCD
28
29
1E
1E
1E
-80E
-667/-53E/-40E
–
3C
32
3C
32
3C
MIN RAS# pulse width, tRAS
30
-80E/-667/-53E
-40E
2D
28
2D
28
2D
28
31
32
256MB, 512MB, 1GB
40
80
01
Module rank density
Address and command setup time, tISb
-80E
-667
-53E
-40E
–
17
20
25
35
17
20
25
35
20
25
35
Address and command hold time, tIHb
33
-80E
-667
-53E
-40E
–
25
27
37
47
25
27
37
47
27
37
47
Data/data mask input setup time, tDSb
Data/data mask input hold time, tDHb
34
35
-80E
-667/-53E
-40E
–
10
15
05
10
15
05
10
15
-80E
-667
-53E
-40E
–
12
17
22
27
12
17
22
27
17
22
27
Write recovery time, tWR
WRITE-to-READ command delay, tWTR
36
37
3C
3C
3C
-80E/-667/-53E
-40E
1E
28
1E
28
1E
28
38
1E
1E
1E
READ-to-PRECHARGE command delay,
tRTP
39
40
00
00
00
Mem analysis probe
-80E
-667/-53E/-40E
–
00
30
00
36
06
Extension for bytes 41 and 42
MIN active auto refresh time, tRC
41
42
-80E
-667/-53E
-40E
–
3C
37
39
3C
37
39
3C
37
69
69
7F
MIN AUTO REFRESH-to-ACTIVE/
AUTO REFRESH command period, tRFC
DDR2 device MAX cycle time, tCKMAX
43
44
80
80
80
-80E
-667
-53E
-40E
–
14
18
1E
23
14
18
1E
23
DDR2 device MAX DQS-DQ skew time,
tDQSQ
18
1E
23
45
-80E
-667
-53E
-40E
–
1E
22
28
2D
1E
22
28
2D
DDR2 device MAX read data hold skew
factor, tQHS
22
28
2D
46
47–61
62
00
00
12
00
00
12
00
00
12
PLL relock time
Optional features, not supported
SPD revision
Release 1.2
63
-80E
-667
-53E
-40E
–
90
4C
F7
5E
31
ED
98
FF
Checksum for bytes 0–62
ED
98
FF
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
18
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