512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Table 13: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
VIH
VIL
1.7
3.6
V
V
Supply voltage
VDDSPD × 0.7
VDDSPD + 0.5
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
–0.6
–
VDDSPD × 0.3
V
VOL
ILI
0.4
3
V
0.10
0.05
1.6
0.4
2
µA
µA
µA
mA
mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current:
ILO
3
ISB
4
ICC
1
Power supply current, READ: SCL clock frequency = 100 KHz
Power supply current, WRITE: SCL clock frequency = 100 KHz
R
ICC
3
W
Table 14: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
Notes
tAA
tBUF
0.2
1.3
200
–
0.9
–
µs
µs
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
tDH
–
ns
tF
300
–
ns
2
SDA and SCL fall time
tHD:DAT
tHD:STA
tHIGH
tI
0
µs
Data-in hold time
0.6
0.6
–
–
µs
Start condition hold time
Clock HIGH period
–
µs
50
–
ns
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
1.3
–
µs
0.3
400
–
µs
2
SDA and SCL rise time
–
KHz
ns
SCL clock frequency
100
0.6
0.6
–
Data-in setup time
–
µs
3
4
Start condition setup time
Stop condition setup time
WRITE cycle time
–
µs
10
ms
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,
the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and
the EEPROM does not respond to its slave address.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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