512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Table 11: EEPROM Device Select Code
The most significant bit (b7) is sent first
Device Type Identifier
Chip Enable
b2
RW
b0
Select Code
b7
b6
b5
b4
b3
b1
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Memory area select code (two arrays)
Protection register select code
Table 12: EEPROM Operating Modes
Mode
RW Bit
WC
Bytes Initial Sequence
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current address READ
Random address READ
Start, device select, RW = 1
Start, device select, RW = 0, address
Restart, device select, RW = 1
1
≥ 1
1
Sequential READ
Byte WRITE
Similar to current or random address READ
Start, device select, RW = 0
VIL
≤ 16
Page WRITE
Start, device select, RW = 0
Figure 7:
SPD EEPROM Timing Diagram
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA In
t
t
t
DH
AA
BUF
SDA Out
UNDEFINED
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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