OBSOLETE
4, 8 MEG x 36
PARITY DRAM SIMMs
READ CYCLE
t
RC
t
t
RAS
RP
V
IH
RAS#
CAS#
V
IL
t
CSH
t
t
RSH
RRH
t
t
t
RCD
CAS
CRP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
ASC
t
ASR
CAH
V
V
IH
IL
ROW
ROW
COLUMN
ADDR
WE#
t
t
RCS
RCH
V
V
IH
IL
t
t
t
t
AA
RAC
CAC
CLZ
t
OFF
V
V
IOH
IOL
DQ
OPEN
OPEN
VALID DATA
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-6
SYMBOL
MIN
MAX
UNITS
ns
SYMBOL
MIN
MAX
UNITS
t
t
AA
30
RAC
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AR
45
0
ns
RAD
15
10
60
110
20
0
t
t
ASC
ns
RAH
t
t
ASR
0
ns
RAS
10,000
t
t
CAC
15
ns
RC
t
t
CAH
10
15
3
ns
RCD
t
t
CAS
10,000
ns
RCH
t
t
CLZ
ns
RCS
0
t
t
CRP
10
60
3
ns
RP
40
0
t
t
CSH
ns
RRH
t
t
OFF
15
ns
RSH
15
4, 8 Meg x 36 Parity DRAM SIMMs
DM45.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
9
MICRON [ MICRON TECHNOLOGY ]
