256Mb: 3V Embedded Parallel NOR Flash
READ Operations
8. For x8, A[MAX:5] address pins should remain unchanged while A[4:0] and A-1 pins are
used to select a byte within the N + 1 byte page. For x16, A[MAX:5] address pins should
remain unchanged while A[4:0] pins are used to select a word within the N + 1 word
page.
9. The following is content for address/data cycles 256 through 258: BAd (FE) - Data; BAd
(FF) - Data; BAd (00) - 29.
10. BLOCK ERASE address cycles can extend beyond six address/data cycles, depending on
the number of blocks to erase.
READ Operations
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors
in the status register. One or three bus WRITE operations can be used to issue the
READ/RESET command.
To return the device to read mode, this command can be issued between bus WRITE
cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET com-
mand is issued during the timeout of a BLOCK ERASE operation, the device requires up
to 10μs to abort, during which time no valid data can be read.
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is valid only when
the device is in read array or auto select mode. One bus WRITE cycle is required to issue
the command.
Once in read CFI mode, bus READ operations will output data from the CFI memory
area. A READ/RESET command must be issued to return the device to the previous
mode (read array or auto select ). A second READ/RESET command is required to put
the device in read array mode from auto select mode.
PDF: 09005aef84bd3b68
m29w_256mb.pdf - Rev. C 7/13 EN
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