M25PX16
Instructions
Table 5.
Instruction set
Description
One-byte instruction Address Dummy
Data
Instruction
code
bytes
bytes
bytes
Read OTP (Read 64 bytes of
OTP area)
ROTP
POTP
0100 1011
4Bh
42h
3
1
1 to 65
1 to 65
Program OTP (Program 64
bytes of OTP area)
0100 0010
3
0
PP
DIFP
SSE
SE
Page Program
0000 0010
1010 0010
0010 0000
1101 1000
1100 0111
1011 1001
02h
A2h
20h
D8h
C7h
B9h
3
3
3
3
0
0
0
0
0
0
0
0
1 to 256
Dual Input Fast Program
Subsector Erase
Sector Erase
1 to 256
0
0
0
0
BE
Bulk Erase
DP
Deep Power-down
Release from Deep Power-
down
RDP
1010 1011
ABh
0
0
0
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input
Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR)
instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
DQ0
DQ1
High Impedance
AI13731
23/65
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