Instructions
M25PX16
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)
after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to
the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read
Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down
(RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted
out.
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or
Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 5.
Instruction set
Description
One-byte instruction Address Dummy
Data
Instruction
code
bytes
bytes
bytes
WREN
WRDI
Write Enable
Write Disable
0000 0110
0000 0100
1001 1111
1001 1110
0000 0101
0000 0001
1110 0101
1110 1000
0000 0011
06h
04h
9Fh
9Eh
05h
01h
E5h
E8h
03h
0
0
0
0
0
0
3
3
3
0
0
0
0
0
0
0
0
0
0
0
1 to 20
1 to 3
1 to ∞
1
RDID
Read Identification
RDSR
WRSR
WRLR
RDLR
READ
Read Status Register
Write Status Register
Write to Lock Register
Read Lock Register
Read Data Bytes
1
1
1 to ∞
Read Data Bytes at higher
speed
FAST_READ
DOFR
0000 1011
0011 1011
0Bh
3Bh
3
3
1
1
1 to ∞
1 to ∞
Dual Output Fast Read
22/65
MICRON [ MICRON TECHNOLOGY ]
