M25PX16 Serial Flash Embedded Memory
Serial Peripheral Interface Modes
Serial Peripheral Interface Modes
The device can be driven by a microcontroller while its serial peripheral interface (SPI)
is in either of the two modes shown here. The difference between the two modes is the
clock polarity when the bus master is in standby mode and not transferring data. Input
data is latched in on the rising edge of the clock, and output data is available from the
falling edge of the clock.
Table 2: SPI Modes
SPI Modes
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
Clock Polarity
C remains at 0 for (CPOL = 0, CPHA = 0)
C remains at 1 for (CPOL = 1, CPHA = 1)
The following figure is an example of three memory devices in a simple connection to
an MCU on an SPI bus. Because only one device is selected at a time, that one device
drives DQ1, while the other devices are HIGH-Z.
Resistors ensure the device is not selected if the bus master leaves S# HIGH-Z. The bus
master might enter a state in which all input/output is HIGH-Z simultaneously, such as
when the bus master is reset. Therefore, the serial clock must be connected to an exter-
nal pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW.
This ensures that S# and the serial clock are not HIGH simultaneously and that
t
SHCH
is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp =
parasitic capacitance of the bus line), is shorter than the time the bus master leaves the
SPI bus in HIGH-Z.
Example:
Cp = 50 pF, that is R × Cp = 5μs. The application must ensure that the bus
master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs. W# and
HOLD# should be driven either HIGH or LOW, as appropriate.
PDF: 09005aef845665a5
m25px16.pdf - Rev. A 11/12 EN
9
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