M25PX16 Serial Flash Embedded Memory
Operating Features
Operating Features
Page Programming
To program one data byte, two commands are required: WRITE ENABLE, which is one
byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by
the internal PROGRAM cycle of duration tPP. To spread this overhead, the PAGE PRO-
GRAM command allows up to 256 bytes to be programmed at a time (changing bits
from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To
optimize timings, it is recommended to use the PAGE PROGRAM command to program
all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM
sequences with each containing only a few bytes.
Dual Input Fast Program
The DUAL INPUT FAST PROGRAM command makes it possible to program up to 256
bytes using two input pins at the same time (by changing bits from 1 to 0). For opti-
mized timings, it is recommended to use the DUAL INPUT FAST PROGRAM command
to program all consecutive targeted bytes in a single sequence than to use several DUAL
INPUT FAST PROGRAM sequences each containing only a few bytes.
Subsector Erase, Sector Erase, Bulk Erase
The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-
ieved a subsector at a time using the SUBSECTOR ERASE command, a sector at a time
using the SECTOR ERASE command, or throughout the entire memory using the BULK
ERASE command. This starts an internal ERASE cycle of duration tSSE, tSE or tBE. The
ERASE command must be preceded by a WRITE ENABLE command.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE).
• WRITE STATUS REGISTER
• PROGRAM OTP
• PROGRAM
• DUAL INPUT FAST PROGRAM
• ERASE (SUBSECTOR ERASE, SECTOR ERASE, BULK ERASE)
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.
When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER
mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS
REGISTER). The device then goes in to the STANDBY POWER mode. The device con-
sumption drops to ICC1
.
PDF: 09005aef845665a5
m25px16.pdf - Rev. A 11/12 EN
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