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M25PX16-VMW6TG 参数 Datasheet PDF下载

M25PX16-VMW6TG图片预览
型号: M25PX16-VMW6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 美光M25PX16串行闪存的嵌入式存储器 [Micron M25PX16 Serial Flash Embedded Memory]
分类和应用: 闪存存储内存集成电路光电二极管PC时钟
文件页数/大小: 56 页 / 732 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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M25PX16 Serial Flash Embedded Memory  
Operating Features  
Table 3: Software Protection Truth Table  
Sector Lock Register  
Bits  
Lock Down Write Lock  
Protection Status  
0
0
1
0
1
0
Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status reversible  
Sector protected from PROGRAM / ERASE / WRITE operations; protection status reversible  
Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status cannot be  
changed except by a power-up.  
1
1
Sector protected from PROGRAM / ERASE / WRITE operations; protection status cannot be  
changed except by a power-up.  
Hardware Data Protection  
Hardware data protection is implemented using the write protect signal applied on the  
W#/VPP pin. This freezes the status register in a read-only mode, protecting the block  
protect (BP) bits and the status register write disable bit (SRWD). The device is ready to  
accept a BULK ERASE command only if all block protect bits are 0.  
Table 4: Sectors 0 to 32, Protected Area Sizes – Upper Area Protection  
Status Register Content  
Memory Content  
Unprotected Area  
Top/Bottom Bit  
BP 2  
BP 1  
BP 0 Protected Area  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none  
All sectors 1  
Upper 32nd (sector 31)  
Upper 16th (sectors 30 to 31)  
Upper 8th (sectors 28 to 31)  
Upper 4th (sectors 24 to 31)  
Upper half (sectors 16 to 31)  
All sectors  
Lower 31/32nds (sectors 0 to 30)  
Lower 15/16ths (sectors 0 to 29)  
Lower 7/8ths (sectors 0 to 27)  
Lower 3/4ths (sectors 0 to 23)  
Lower half (sectors 0 to 15)  
none  
All sectors  
none  
1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0.  
Note:  
Table 5: Sectors 0 to 32, Protected Area Sizes – Lower Area Protection  
Status Register Content  
Memory Content  
Top/Bottom Bit  
BP 2  
BP 1  
BP 0 Protected Area  
Unprotected Area  
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
none  
All sectors 1  
Lower 32nd (sector 0)  
Lower 16th (sectors 0 to 1)  
Lower 8th (sectors 0 to 3)  
Lower 4th (sectors 0 to 7)  
Lower half (sectors 0 to 15)  
All sectors  
Upper 31/32nds (sectors 1 to 31)  
Upper 15/16ths (sectors 2 to 31)  
Upper 7/8ths (sectors 4 to 31)  
Upper 3/4ths (sectors 8 to 31)  
Upper half (sectors 16 to 31)  
none  
PDF: 09005aef845665a5  
m25px16.pdf - Rev. A 11/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
13  
© 2012 Micron Technology, Inc. All rights reserved.