Micron M25P32 Serial Flash Embedded Memory
Operating Features
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific commands. For a detailed description of the status register
bits, see READ STATUS REGISTER (page 21).
Data Protection by Protocol
Non-volatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and WRITE STATUS REGISTER commands are checked before they
are accepted for execution to ensure they consist of a number of clock pulses that is a
multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit.
In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-
fers extra software protection since all WRITE, PROGRAM, and ERASE commands are
ignored when the device is in this mode.
Software Data Protection
Software data protection is achieved as follows:
Memory can be configured as read-only using the block protect bits (BP2, BP1, BP0) as
shown in the Protected Area Sizes table.
Hardware Data Protection
Hardware data protection is implemented using the write protect signal applied on the
W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-
tect bits (BP2, BP1, BP0) and the status register write disable bit (SRWD) are protected.
Table 3: Protected Area Sizes
Status Register Content
Memory Content
BP Bit 2
BP Bit 1
BP Bit 0
Protected Area
Unprotected Area
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
All sectors (sectors 0 to 63)
Lower 63/64ths (sectors 0 to 62)
Lower 31/32nds (sectors 0 to 61)
Lower 15/16ths (sectors 0 to 59)
Lower 7/8ths (sectors 0 to 55)
Lower 3/4ths (sectors 0 to 47)
Lower half (sectors 0 to 31)
none
Upper 64th (sector 63)
Upper 32nd (sectors 62 and 63)
Upper 16th (sectors 60 and 63)
Upper 8th (sectors 56 to 63)
Upper 4th (sectors 48 to 63)
Upper half (sectors 32 to 63)
All sectors (sectors 0 to 63)
1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP2, BP1, BP0) are 0.
Note:
PDF: 09005aef84566541
m25p32.pdf - Rev. M 9/11 EN
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