Micron M25P32 Serial Flash Embedded Memory
SPI Modes
Figure 5: Bus Master and Memory Devices on the SPI Bus
V
SS
V
CC
R
SDO
SDI
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SCK
C
V
V
V
CC
C
C
CC
CC
V
V
V
SS
SS
SS
SPI Bus Master
DQ1 DQ0
DQ1 DQ0
DQ1 DQ0
SPI memory
device
SPI memory
device
SPI memory
device
R
R
R
CS3
CS2
CS1
W#
HOLD#
S#
S#
W# HOLD#
S#
W#
HOLD#
1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.
Notes:
2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the
S# line HIGH-Z.
3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for exam-
ple, when the bus master is reset. Therefore, the C must be connected to an external
pull-down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled
LOW. This ensures that S# and C do not go HIGH at the same time and that the tSHCH
requirement is met.
4. The typical value of R is 100 kΩ, assuming that the time constant R × Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves
the SPI bus HIGH-Z.
5. Example: Given that Cp = 50 pF (R × Cp = 5μs), the application must ensure that the bus
master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs.
PDF: 09005aef84566541
m25p32.pdf - Rev. M 9/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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