Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 44: Protection Register Information
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+E)h
1
3F:
--01
01
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user-programmable. Bits 0-15 point
to the protection register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
40:
41:
42:
43:
--80
--00
--03
--03
80h
00h
8bytes
8bytes
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
Note:
1.
The variable P is a pointer which is defined at CFI offset 15h.
Table 45: Burst Read Information
Offset(1)
Length
Description
(Optional Flash Features and Commands)
Hex
Code
Add.
Value
P = 31h
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of read-
page bytes. See offset 28h for device word width to determine page-
mode data output width. 00h indicates no read page buffer.
(P+13)h
1
1
44:
45:
--04
--00
16 byte
0
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
(P+14)h
Synchronous Mode Read Capability Configuration 1
Bits 3-7 = Reserved
bits 0-2 = “n” such that 2n+1 HEX value represents the maximum
number of continuous synchronous burst reads when the device is
configured for its maximum word width. A value of 07h indicates that
the device is capable of continuous linear bursts until that will output
data until the internal burst counter reaches the end of the device’s
burstable address space. This field’s 3-bit value can be written directly
to the Read Configuration Register Bits 0-2 if the device is configured for
its maximum word width. See offset 1Fh for word width to determine
the burst data output width.
(P+15)h
1
46:
--00
n/a
(P+16h)h
(P+45h)h
Note:
1
1
Synchronous Mode Read Capability Configuration 2
J3C mark for VIL fix for customers
47:
76:
--00
--01
n/a
01
1.
The variable P is a pointer which is defined at CFI offset 15h.
Jan 2011
208032-03
Datasheet
63
MICRON [ MICRON TECHNOLOGY ]
