Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 41: Device Geometry Definition (Sheet 2 of 2)
Offset
Length
Description
Erase Block Region 1 Information
Code See Table Below
2D:
2E:
2F:
30:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2Dh
4
Notes:
1.
Compatible with J3 130nm device (32 bytes). J3 65 nm SBC device supports up to maximum 256 words (x16 mode)/
256 bytes (x8 mode) buffer write.
Table 42: Device Geometry: Address Codes
Address
32 Mbit
64 Mbit
128 Mbit
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
--16
--02
--00
--05
--00
--01
--1F
--00
--00
--02
--17
--02
--00
--05
--00
--01
--3F
--00
--00
--02
--18
--02
--00
--05
--00
--01
--7F
--00
--00
--02
13.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific
Extended Query table specifies this and other similar information.
Table 43: Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
3
Primary extended query table
31:
32:
33:
34:
35:
--50
--52
--49
--31
--31
“P”
“R”
“I”
Unique ASCII string “PRI”
1
1
Major version number, ASCII
Minor version number, ASCII
“1”
“1”
Jan 2011
208032-03
Datasheet
61
MICRON [ MICRON TECHNOLOGY ]
