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JS28F512P30TF 参数 Datasheet PDF下载

JS28F512P30TF图片预览
型号: JS28F512P30TF
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 92 页 / 1225 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, 1Gb, 2Gb: P30-65nm  
Common Flash Interface  
Table 23: Primary Vendor-Specific Extended Query (Continued)  
Hex Offset  
ASCII Value  
P = 10Ah  
Length  
Description  
Address Hex Code  
(DQ[7:0])  
(P+D)h  
1
VPP optimum program/erase voltage.  
bits 0 - 3 BCD 100mV  
117:  
- -90  
9.0V  
bits 4 - 7 hex value in volts  
1. See Optional Features Fields table.  
Note:  
Table 24: Optional Features Field  
Discrete  
2Gb  
Address  
Bottom  
Top  
Bottom  
Top  
die 1 (B)  
40:  
die 2 (T)  
--00  
die 1 (T)  
--40  
die 2 (B)  
--00  
112:  
--00  
--00  
Table 25: One Time Programmable (OTP) Space Information  
Hex Offset  
Hex  
Code  
ASCII Value  
(DQ[7:0])  
P = 10Ah  
Length  
Description  
Address  
(P+E)h  
1
Number of OTP block fields in JEDEC ID space.  
00h indicates that 256 OTP fields are available.  
118:  
- -02  
2
OTP Field 1: OTP Description:  
119:  
11A:  
1B:  
- -80  
- -00  
- -03  
- -03  
80h  
00h  
This field describes user-available OTP bytes.  
Some are preprogrammed with device-unique se-  
rial numbers. Others are user-programmable.  
Bits 0-15 point to the OTP Lock byte (the first  
byte).  
8 byte  
8 byte  
11C:  
(P+F)h  
(P+10)h  
(P+11)h  
(P+12)h  
The following bytes are factory preprogrammed  
and user-programmable:  
Bits 0 - 7 = Lock/bytes JEDEC plane physical low  
address.  
4
Bits 8 - 15 = Lock/bytes JEDEC plane physical high  
address.  
Bits 16 - 23 = n where 2n equals factory preprog-  
rammed bytes.  
Bits 24 - 31 = n where 2n equals user-programma-  
ble bytes.  
PDF: 09005aef845667b3  
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
54  
© 2013 Micron Technology, Inc. All rights reserved.  
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