512Mb, 1Gb, 2Gb: P30-65nm
Program Operations
With adequate continuity testing, programming equipment can rely on the device’s in-
ternal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
Table 10: BEFP Requirements
Parameter/Issue
Case temperature
VCC
Requirement
Notes
TC = 30°C ± 10°C
Nominal VCC
VPP
Driven to VPPH
Setup and confirm
Programming
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
Buffer alignment
WA0 must align with the start of an array buffer boundary.
1
1. Word buffer boundaries in the array are determined by the lowest 9 address bits (0x000
through 0x1FF). The alignment start point is 0x000.
Note:
Table 11: BEFP Considerations
Parameter/Issue
Requirement
Notes
Cycling
For optimum performance, cycling must be limited below 50 ERASE cycles per block.
1
2
Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block.
Suspend BEFP cannot be suspended.
Programming the ar- Programming to the array can occur only when the buffer is full.
ray
3
1. Some degradation in performance may occur if this limit is exceeded, but the internal
algorithm continues to work properly.
Notes:
2. If the internal address counter increments beyond the block's maximum address, ad-
dressing wraps around to the beginning of the block.
3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.
BEFP Setup Phase: After receiving the BEFP SETUP and CONFIRM command se-
quence, SR7 (ready) is cleared, indicating that the device is busy with BEFP algorithm
startup. A delay before checking SR7 is required to allow the device enough time to per-
form all of its setups and checks (block lock status, VPP level, etc.). If an error is detected,
SR4 is set and BEFP operation terminates. If the block was found to be locked, SR1 is
also set. SR3 is set if the error occurred due to an incorrect VPP level.
Note: Reading from the device after the BEFP SETUP and CONFIRM command se-
quence outputs status register data. Do not issue the READ STATUS REGISTER com-
mand; it will be interpreted as data to be loaded into the buffer.
BEFP Program/Verify Phase: After the BEFP setup phase has completed, the host pro-
gramming system must check SR[7,0] to determine the availability of the write buffer
for data streaming. SR7 cleared indicates the device is busy and the BEFP program/veri-
fy phase is activated. SR0 indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
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p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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