256Mb and 512Mb (256Mb/256Mb), P30-65nm
Power and Reset Specifications
Power and Reset Specifications
VCC should attain VCCmin from VSS simultaneously with or before applying VCCQ, VPP
during power up. VCC should attain VSS during power down. Device inputs should not
be driven before supply voltage = VCCmin
.
Power supply transitions should only occur when RST# is LOW. This protects the device
from accidental programming or erasure during power transitions.
Asserting RST# during a system reset is important with automated program/erase devi-
ces because systems typically expect to read from the device when coming out of reset.
If a CPU reset occurs without a device reset, proper CPU initialization may not occur.
This is because the device may be providing status information, instead of array data as
expected. Connect RST# to the same active LOW reset signal used for CPU initialization.
Because the device is disabled when RST# is asserted, it ignores its control inputs dur-
ing power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 37: Power and Reset
Parameter
Symbol
tPLPH
tPLPH
Min
100
–
Max
–
Unit
ns
Notes
RST# pulse width LOW
1, 2, 3, 4
1, 3, 4, 7
1, 3, 4, 7
1, 4, 5, 6
RST# LOW to device reset during erase
RST# LOW to device reset during program
VCC Power valid to RST# de-assertion (HIGH)
25
25
–
us
–
tVCCPH
300
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
Notes:
3. Not applicable if RST# is tied to VCC
4. Sampled, but not 100% tested.
.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC
≥
VCCMIN
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC
VCCMIN
.
≥
.
7. Reset completes within tPLPH if RST# is asserted while no ERASE or PROGRAM operation
is executing.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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77
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