256Mb and 512Mb (256Mb/256Mb), P30-65nm
Bus Operations
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal ad-
dress latches. OE# low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and
RST# must be VIH; CE# must be VIL).
Bus cycles to/from the P30-65nm device conform to standard microprocessor bus oper-
ations. The Bus Operations table shows the bus operations and the logic levels that
must be applied to the device control signal inputs.
Table 9: Bus Operations
Bus Operation
RST#
VIH
VIH
VIH
VIH
VIH
VIL
CLK
ADV#
CE#
L
OE#
L
WE#
H
WAIT
Deasserted
Driven
DQ[15:0] Notes
Read
Asynchronous
Synchronous
Write
X
L
L
Output
Output
Input
1
Running
L
L
H
X
X
X
X
L
L
H
L
High-Z
1, 2
1
Output Disable
X
X
X
L
H
H
High-Z
High-Z
High-Z
High-Z
Standby
Reset
H
X
X
X
High-Z
1
X
X
High-Z
1, 3
1. X = Don’t Care (H or L).
Notes:
2. Refer to the Command Bus Cycles table for valid DQ[15:0] during a write operation.
3. RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
Reads
Writes
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are
asserted. CE# is the device-select control. When asserted, it enables the flash memory
device. OE# is the data-output control. When asserted, the addressed flash memory da-
ta is driven onto the I/O bus.
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge of
WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the bus cycle
sequence for each of the supported device commands, while the Command Codes and
Definitions table describes each command.
Note: Write operations with invalid VCC and/or VPP voltages can produce spurious re-
sults and should not be attempted.
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-im-
pedance (High-Z) state, WAIT is also placed in High-Z.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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