256Mb and 512Mb (256Mb/256Mb), P30-65nm
Signals
Signals
Table 7: TSOP and Easy BGA Signal Descriptions
Symbol
Type
Name and Function
A[MAX:1]
Input
Address inputs: Device address inputs. 256Mb: A[24:1]; 512Mb: A[25:1]. Note: The virtual
selection of the 256Mb top parameter die in the dual-die 51Mb configuration is accom-
plished by setting A25 HIGH (VIH).
Note: The active address pins unused in design should not be left floating; tie them to
VCCQ or VSS according to specific design requirements.
DQ[15:0]
ADV#
Input/Output Data input/output: Inputs data and commands during write cycles; outputs data during
memory, status register, protection register, and read configuration register reads. Data
balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.
Input
Address valid: Active LOW input. During synchronous READ operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-
ever occurs first.
In asynchronous mode, the address is latched when ADV# goes HIGH or continuously flows
through if ADV# is held LOW.
Note: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CE#
CLK
Input
Input
Chip enable: Active LOW input. CE# LOW selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are ac-
tive. When de-asserted, the associated flash die is deselected, power is reduced to standby
levels, data and wait outputs are placed in High-Z state.
Note: Chip enable must be driven HIGH when device is not in use.
Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.
During synchronous READs, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# LOW, whichever occurs first.
Note:Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OE#
Input
Input
Output enable: Active LOW input. OE# LOW enables the device’s output data buffers
during read cycles. OE# HIGH places the data outputs and WAIT in High-Z.
RST#
Reset: Active LOW input. RST# resets internal automation and inhibits WRITE operations.
This provides data protection during power transitions. RST# HIGH enables normal opera-
tion. Exit from reset places the device in asynchronous read array mode.
WAIT
Output
Wait: Indicates data valid in synchronous array or non-array burst reads. Read Configura-
tion Register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active
output is VOL or VOH when CE# and OE# are VIL. WAIT is High-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, this signal indicates invalid data when as-
serted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, this signal is de-asserted.
WE#
WP#
Input
Input
Write enable: Active LOW input. WE# controls writes to the device. Address and data are
latched on the rising edge of WE# or CE#, whichever occurs first.
Write protect: Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in
lock-down cannot be unlocked with the Unlock command. WP# HIGH overrides the lock-
down function enabling blocks to be erased or programmed using software commands.
Note: Designs not using WP# for protection could tie it to VCCQ or VSS without additional
capacitor.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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