256Mb and 512Mb (256Mb/256Mb), P30-65nm
Device Command Bus Cycles
2. ID = Identifier data; CFI-D = CFI data on DQ[15:0]; SRD = Status register data; WD = Word
data; N = Word count of data to be loaded into the write buffer; OTP-D = Protection
register data; LRD = Lock register data.
3. The second cycle of the BUFFERED PROGRAM command is the word count of the data to
be loaded into the write buffer. This is followed by up to 512 words of data. Then the
CONFIRM command (0xD0) is issued, triggering the array programming operation.
4. The CONFIRM command (0xD0) is followed by the buffer data.
5. The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 512.
The subsequent cycles load data words into the program buffer at a specified address
until word count is achieved, after the data words are loaded, the final cycle is the con-
firm cycle 0xD0).
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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