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JS28F256P30TFE 参数 Datasheet PDF下载

JS28F256P30TFE图片预览
型号: JS28F256P30TFE
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB和512MB (256 / 256MB ) , P30-65nm [256Mb and 512Mb (256Mb/256Mb), P30-65nm]
分类和应用:
文件页数/大小: 95 页 / 1351 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Device Command Codes  
Table 10: Command Codes and Definitions (Continued)  
Mode  
Code  
Device Mode  
Description  
Protection  
0x60  
Block lock Setup  
First cycle of a 2-cycle command; prepares the CUI for block lock config-  
uration changes. If the next command is not Block Lock (0x01), Block  
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register  
bits SR.5 and SR.4, indicating a command sequence error.  
0x01  
0xD0  
Block lock  
If the previous command was Block Lock Setup (0x60), the addressed  
block is locked.  
Block Unlock  
If the previous command was Block Lock Setup (0x60), the addressed  
block is unlocked. If the addressed block is in a lock-down state, the  
operation has no effect.  
0x2F  
0xC0  
Block Lock-Down  
If the previous command was Block Lock Setup (0x60), the addressed  
block is locked down.  
OTP Register or Lock First cycle of a 2-cycle command; prepares the device for a OTP register  
Register program  
setup  
or Lock Register program operation. The second cycle latches the regis-  
ter address and data, and starts the programming algorithm to pro-  
gram data the the OTP array.  
Configuration  
0x60  
0x03  
Read Configuration First cycle of a 2-cycle command; prepares the CUI for device read con-  
Register Setup  
figuration. If the Set Read Configuration Register command (0x03) is  
not the next command, the CUI sets Status Register bits SR.4 and SR.5,  
indicating a command sequence error.  
Read Configuration If the previous command was Read Configuration Register Setup  
Register  
(0x60), the CUI latches the address and writes A[16:1] to the Read Con-  
figuration Register for Easy BGA and TSOP, A[15:0] for QUAD+. Follow-  
ing a Configure Read Configuration Register command, subsequent  
read operations access array data.  
Blank Check  
0xBC  
0xD0  
0xEB  
Block Blank Check  
First cycle of a 2-cycle command; initiates the Blank Check operation on  
a main block.  
Block Blank Check  
Confirm  
Second cycle of blank check command sequence; it latches the block  
address and executes blank check on the main array block.  
EFI  
Extended Function  
First cycle of a multiple-cycle command; initiate operation using exten-  
Interface command ded function interface. The second cycle is a Sub-Op-Code, the data  
written on third cycle is one less than the word count; the allowable  
value on this cycle are 0–511. The subsequent cycles load data words in-  
to the program buffer at a specified address until word count is ach-  
ieved.  
PDF: 09005aef84566799  
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
27  
© 2013 Micron Technology, Inc. All rights reserved.  
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