256Mb and 512Mb (256Mb/256Mb), P30-65nm
Signals
Table 8: QUAD+ SCSP Signal Descriptions (Continued)
Symbol
Type
Name and Function
CLK
Input
Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.
During synchronous READ operations, addresses are latched on the rising edge of ADV#,
or on the next valid CLK edge with ADV# LOW, whichever occurs first.
Note: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
F1-OE#
RST#
Input
Input
Output enable: Active LOW input. OE# LOW enables the device’s output data buffers
during read cycles. OE# HIGH places the data outputs and wait in High-Z.
Reset: Active LOW input. RST# resets internal automation and inhibits WRITE operations.
This provides data protection during power transitions. RST# HIGH enables normal opera-
tion. Exit from reset places the device in asynchronous read array mode.
WAIT
Output
Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-
tion register bit 10 (RCR.10, WT) determines its polarity when asserted. The active output is
VOL or VOH when CE# and OE# are VIL. WAIT is High-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asser-
ted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, WAIT is de-asserted.
WE#
WP#
Input
Input
Write enable: Active LOW input. WE# controls writes to the device. Address and data are
latched on the rising edge of WE# or CE#, whichever occurs first.
Write protect: Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in
lock-down cannot be unlocked with the UNLOCK command. WP# HIGH overrides the lock-
down function enabling blocks to be erased or programmed using software commands.
Note: Designs not using WP# for protection could tie it to VCCQ or VSS without additional
capacitor.
VPP
Power/lnput Erase and program power: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid
VPP voltages should not be attempted.
Set VPP = VPPL for in-system PROGRAM and ERASE operations. To accommodate resistor or
diode drops from the system supply, the VIH level of VPP can be as low as VPPL,min . VPP must
remain above VPPL,min to perform in-system flash modification. VPP may be 0V during READ
operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for
2500 cycles. VPP can be connected to 9V for a cumulative total not to exceed 80 hours. Ex-
tended use of this pin at 9V may reduce block cycling capability.
VCC
Power
Device core power supply: Core (logic) source voltage. Writes to the flash array are in-
hibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
VSS
Power
Power
—
Output power supply: Output driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
RFU
Reserved for future use: Reserved by Micron for future device functionality and en-
hancement. These should be treated in the same way as a Do Not Use (DNU) signal.
DU
NC
—
—
Do not use: Do not connect to any other signal, or power supply; must be left floating.
No connect: No internal connection; can be driven or floated.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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