256Mb and 512Mb (256Mb/256Mb), P30-65nm
Signals
Table 7: TSOP and Easy BGA Signal Descriptions (Continued)
Symbol
Type
Name and Function
VPP
Power/Input Erase and program power: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid
VPP voltages should not be attempted.
Set VPP = VPPL for in-system PROGRAM and ERASE operations. To accommodate resistor or
diode drops from the system supply, the VIH level of VPP can be as low as VPPL,min . VPP must
remain above VPPL,min to perform in-system flash modification. VPP may be 0V during READ
operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for
2500 cycles. VPP can be connected to 9V for a cumulative total not to exceed 80 hours. Ex-
tended use of this pin at 9V may reduce block cycling capability.
VCC
Power
Device core power supply: Core (logic) source voltage. Writes to the flash array are in-
hibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
VSS
Power
Power
—
Output power supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
RFU
Reserved for future use: Reserved by Micron for future device functionality and en-
hancement. These should be treated in the same way as a Do Not Use (DNU) signal.
DU
NC
—
—
Do not use: Do not connect to any other signal, or power supply; must be left floating.
No connect: No internal connection; can be driven or floated.
Table 8: QUAD+ SCSP Signal Descriptions
Symbol
Type
Name and Function
A[MAX:0]
Input
Address inputs: Device address inputs. 256Mb: A[23:0]; 512Mb: A[24:0]. Note: The virtual
selection of the 256Mb top parameter die in the dual-die 512Mb configuration is accom-
plished by setting A24 HIGH (VIH).
Note: The address pins unused in design should not be left floating; tie them to VCCQ or
VSS according to specific design requirements.
DQ[15:0]
ADV#
Input/Output Data input/output: Inputs data and commands during write cycles; outputs data during
memory, status register, protection register, and read configuration register reads. Data
balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.
Input
Address valid: Active LOW input. During synchronous READ operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-
ever occurs first.
In asynchronous mode, the address is latched when ADV# goes HIGH or continuously flows
through if ADV# is held LOW.
Note: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
F1-CE#
Input
Flash chip enable: Active LOW input. CE# LOW selects the associated flash memory die.
When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers
are active. When de-asserted, the associated flash die is deselected, power is reduced to
standby levels, data and wait outputs are placed in High-Z state.
Note: Chip enable must be driven HIGH when device is not in use.
PDF: 09005aef84566799
p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN
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