PIC24FJ64GA104 FAMILY
EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)
TAD
TCY
ADCS =
– 1
TAD = TCY • (ADCS + 1)
Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
FIGURE 21-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD
RIC 250
RSS 5 k(Typical)
Sampling
Switch
VT = 0.6V
VT = 0.6V
ANx
RSS
Rs
CHOLD
= ADC capacitance
= 4.4 pF (Typical)
VA
CPIN
ILEAKAGE
500 nA
6-11 pF
(Typical)
VSS
Legend: CPIN
VT
= Input Capacitance
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
CHOLD
Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 5 k.
2010 Microchip Technology Inc.
DS39951C-page 227
MICROCHIP [ MICROCHIP ]
