PIC18F2420/2520/4420/4520
TABLE 5-2:
PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR2
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
0000 0000 51, 206
0000 0000 51, 206
0000 0000 51, 213
0000 0000 51, 211
0000 0010 51, 202
0000 000x 51, 203
0000 0000 51, 74, 83
0000 0000 51, 74, 83
0000 0000 51, 74, 83
xx-0 x000 51, 75, 84
11-1 1111 52, 101
00-0 0000 52, 97
00-0 0000 52, 99
1111 1111 52, 100
0000 0000 52, 96
0000 0000 52, 98
0q-0 0000 27, 52
0000 -111 52, 118
1111 1111 52, 114
1111 1111 52, 111
1111 1111 52, 108
1111 1111 52, 105
---- -xxx 52, 117
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
EEPGD
OSCFIP
OSCFIF
OSCFIE
PSPIP(2)
PSPIF(2)
PSPIE(2)
INTSRC
IBF
CFGS
CMIP
CMIF
CMIE
ADIP
—
—
FREE
EEIP
WRERR
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
WREN
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
WR
RD
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
PIR2
—
EEIF
PIE2
—
EEIE
IPR1
RCIP
RCIF
RCIE
—
TXIP
PIR1
ADIF
TXIF
PIE1
ADIE
PLLEN(3)
TXIE
OSCTUNE
TRISE(2)
TRISD(2)
TRISC
TRISB
TUN4
PSPMODE
OBF
IBOV
TRISE2
TRISE1
TRISE0
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
TRISA
LATE(2)
TRISA7(5)
TRISA6(5) PORTA Data Direction Register
—
—
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
LATD(2)
LATC
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 52, 114
xxxx xxxx 52, 111
xxxx xxxx 52, 108
xxxx xxxx 52, 105
---- xxxx 52, 117
xxxx xxxx 52, 114
xxxx xxxx 52, 111
xxxx xxxx 52, 108
xx0x 0000 52, 105
LATB
LATA
LATA7(5)
LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch)
PORTE
PORTD(2)
PORTC
PORTB
PORTA
—
—
—
—
RE3(4)
RD3
RC3
RB3
RE2(2)
RD2
RC2
RB2
RE1(2)
RD1
RC1
RB1
RE0(2)
RD0
RC0
RB0
RD7
RD6
RC6
RB6
RD5
RC5
RB5
RA5
RD4
RC4
RB4
RA4
RC7
RB7
RA7(5)
RA6(5)
RA3
RA2
RA1
RA0
Legend:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
DS39631E-page 66
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
