PIC18F2420/2520/4420/4520
TABLE 5-2:
PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 50, 125
xxxx xxxx 50, 125
1111 1111 50, 123
0100 q000 30, 50
0-00 0101 50, 245
--- ---0 50, 259
TMR0L
T0CON
TMR0ON
IDLEN
VDIRMAG
—
T08BIT
IRCF2
—
T0CS
IRCF1
IRVST
—
T0SE
IRCF0
HLVDEN
—
PSA
OSTS
HLVDL3
—
T0PS2
IOFS
HLVDL2
—
T0PS1
SCS1
HLVDL1
—
T0PS0
SCS0
OSCCON
HLVDCON
WDTCON
RCON
HLVDL0
SWDTEN
BOR
—
IPEN
SBOREN(1)
—
RI
TO
PD
POR
0q-1 11q0 42, 48,
102
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Bytes
xxxx xxxx 50, 132
xxxx xxxx 50, 132
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0000 0000 50, 127
0000 0000 50, 134
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
MSSP Receive Buffer/Transmit Register
1111 1111 50, 134
T2CON
SSPBUF
—
T2CKPS0 -000 0000 50, 133
xxxx xxxx 50, 169,
170
SSPADD
SSPSTAT
MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode.
0000 0000 50, 170
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 50, 162,
171
SSPCON1
SSPOV
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 50, 163,
172
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
ACKSTAT
ACKEN
0000 0000 50, 173
xxxx xxxx 51, 232
xxxx xxxx 51, 232
--00 0000 51, 223
--00 0qqq 51, 224
0-00 0000 51, 225
xxxx xxxx 51, 140
xxxx xxxx 51, 140
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 51, 139,
147
CCPR2H
CCPR2L
CCP2CON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CMCON
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 51, 140
xxxx xxxx 51, 140
—
—
DC2B1
RXDTP
PDC5(2)
ECCPAS1
CVRR
DC2B0
TXCKP
PDC4(2)
ECCPAS0
CVRSS
C1INV
CCP2M3
BRG16
PDC3(2)
PSSAC1
CVR3
CCP2M2
—
PDC2(2)
PSSAC0
CVR2
CM2
CCP2M1
WUE
PDC1(2)
CCP2M0 --00 0000 51, 139
ABDOVF
PRSEN
ECCPASE
CVREN
C2OUT
RCIDL
ABDEN
PDC0(2)
0100 0-00 51, 204
PDC6(2)
ECCPAS2
CVROE
C1OUT
0000 0000 51, 156
PSSBD1(2) PSSBD0(2) 0000 0000 51, 157
CVR1
CM1
CVR0
CM0
0000 0000 51, 239
0000 0111 51, 233
xxxx xxxx 51, 137
xxxx xxxx 51, 137
C2INV
CIS
TMR3H
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000 51, 135
Legend:
Note 1:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
© 2008 Microchip Technology Inc.
DS39631E-page 65
MICROCHIP [ MICROCHIP ]
