PIC18F2420/2520/4420/4520
The SFRs can be classified into two sets: those asso-
ciated with the “core” device functionality (ALU, Resets
and interrupts) and those related to the peripheral func-
tions. The Reset and Interrupt registers are described
in their respective chapters, while the ALU’s STATUS
register is described later in this section. Registers
related to the operation of a peripheral feature are
described in the chapter for that peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1:
Address
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2420/2520/4420/4520 DEVICES
Name
Address
Name
Address
FBFh
FBEh
Name
Address
F9Fh
Name
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TOSU
TOSH
FDFh
INDF2(1)
CCPR1H
CCPR1L
IPR1
PIR1
PIE1
FDEh POSTINC2(1)
FDDh POSTDEC2(1)
FDCh PREINC2(1)
FDBh PLUSW2(1)
F9Eh
F9Dh
F9Ch
TOSL
FBDh CCP1CON
(2)
STKPTR
PCLATU
PCLATH
PCL
FBCh
FBBh
CCPR2H
CCPR2L
—
F9Bh OSCTUNE
(2)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FSR2H
FSR2L
FBAh CCP2CON
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
—
—
—
—
(2)
(2)
(2)
(2)
FB9h
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(1)
STATUS
TMR0H
TMR0L
T0CON
FB8h BAUDCON
FB7h PWM1CON(3)
FB6h ECCP1AS(3)
TRISE(3)
TRISD(3)
TRISC
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
CVRCON
CMCON
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
(2)
—
OSCCON
TRISB
FD2h HLVDCON
TRISA
(2)
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
WDTCON
RCON
—
(2)
—
(2)
TMR1H
—
FEEh POSTINC0(1)
FEDh POSTDEC0(1)
FECh PREINC0(1)
FEBh PLUSW0(1)
TMR1L
—
(2)
T1CON
LATE(3)
LATD(3)
LATC
TMR2
PR2
RCSTA
(2)
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(1)
FE5h POSTDEC1(1)
FE4h PREINC1(1)
FE3h PLUSW1(1)
FSR0H
FSR0L
WREG
INDF1(1)
T2CON
—
LATB
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
EEADR
LATA
(2)
EEDATA
—
FA7h EECON2(1)
—
(2)
(2)
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EECON1
—
(2)
(2)
—
—
(2)
—
PORTE(3)
PORTD(3)
PORTC
PORTB
(2)
—
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
PORTA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 28-pin devices.
© 2008 Microchip Technology Inc.
DS39631E-page 63
MICROCHIP [ MICROCHIP ]
