PIC18F2420/2520/4420/4520
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision A (June 2004)
Original data sheet for PIC18F2420/2520/4420/4520
devices.
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Revision B (January 2007)
This revision includes updates to the packaging
diagrams.
Revision C (June 2007)
This revision includes updates to
Section 6.0 “Flash
Program Memory”, Section 23.0 “Special Features
of the CPU”, Section 26.0 “Electrical Characteris-
tics”
and minor corrections applicable to Timer1,
EUSART and the packaging diagrams. Also added the
125°C specifications.
Revision D (July 2007)
This revision updated the extended temperature
information in
Revision E (October 2008)
This revision updated
and
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2420
16384
8192
19
Ports A, B, C, (E)
2
0
No
10 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
PIC18F2520
32768
16384
19
Ports A, B, C, (E)
2
0
No
10 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
PIC18F4420
16384
8192
20
Ports A, B, C, D, E
1
1
Yes
13 Input Channels
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
PIC18F4520
32768
16384
20
Ports A, B, C, D, E
1
1
Yes
13 Input Channels
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
I/O Ports
Capture/Compare/PWM Modules
Enhanced
Capture/Compare/PWM Modules
Parallel Communications (PSP)
10-Bit Analog-to-Digital Module
Packages
©
2008 Microchip Technology Inc.
DS39631E-page 395
MICROCHIP [ MICROCHIP TECHNOLOGY ]
