PIC18F2420/2520/4420/4520
FIGURE 26-22:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
Data Hold after CK ↓ (DT hold time)
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2420/2520/4420/4520 (INDUSTRIAL)
PIC18LF2420/2520/4420/4520 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
—
—
—
—
10
<±1
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
<±1
—
—
<±2.0
<±1
Gain Error
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
1.8
3
—
—
—
—
V
V
VDD < 3.0V
VDD ≥ 3.0V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
kΩ
A40
A50
IAD
A/D Current from PIC18FXXXX
—
—
180
90
—
—
μA Average current during
μA
VDD
conversion
PIC18LFXX20
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
DS39631E-page 358
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
