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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)  
Param.  
Symbol  
Characteristic  
Min  
Max Units  
Conditions  
No.  
100  
THIGH  
Clock High Time  
100 kHz mode  
4.0  
0.6  
μs  
μs  
400 kHz mode  
MSSP module  
100 kHz mode  
400 kHz mode  
MSSP module  
1.5 TCY  
4.7  
101  
TLOW  
Clock Low Time  
μs  
μs  
1.3  
1.5 TCY  
102  
103  
TR  
TF  
SDA and SCL Rise 100 kHz mode  
Time  
1000  
ns  
ns  
400 kHz mode  
20 + 0.1 CB 300  
CB is specified to be from  
10 to 400 pF  
SDA and SCL Fall 100 kHz mode  
Time  
300  
ns  
ns  
400 kHz mode  
20 + 0.1 CB 300  
CB is specified to be from  
10 to 400 pF  
90  
TSU:STA Start Condition  
Setup Time  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
4.7  
0.6  
4.0  
0.6  
0
μs  
μs  
μs  
μs  
ns  
μs  
ns  
ns  
μs  
μs  
ns  
ns  
μs  
μs  
Only relevant for Repeated  
Start condition  
91  
THD:STA Start Condition  
Hold Time  
After this period, the first  
clock pulse is generated  
106  
107  
92  
THD:DAT Data Input Hold  
Time  
0
0.9  
TSU:DAT Data Input Setup  
Time  
250  
100  
4.7  
0.6  
(Note 2)  
TSU:STO Stop Condition  
Setup Time  
109  
110  
TAA  
Output Valid from  
Clock  
3500  
(Note 1)  
TBUF  
Bus Free Time  
4.7  
1.3  
Time the bus must be free  
before a new transmission  
can start  
D102  
CB  
Bus Capacitive Loading  
400  
pF  
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region  
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement  
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the  
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must  
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the  
Standard mode I2C bus specification), before the SCL line is released.  
DS39631E-page 354  
© 2008 Microchip Technology Inc.  
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