PIC18F2420/2520/4420/4520
FIGURE 26-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18FXXXX
0.7
1.4
25.0(1)
25.0(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX
—
—
11
1
3
μs A/D RC mode
μs VDD = 2.0V; A/D RC mode
TAD
PIC18LFXXXX
131
TCNV
Conversion Time
12
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
132
135
TBD
TACQ
TSWC
TDIS
1.4
—
—
(Note 4)
—
μs -40°C to +85°C
Switching Time from Convert → Sample
Discharge Time
0.2
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
© 2008 Microchip Technology Inc.
DS39631E-page 359
MICROCHIP [ MICROCHIP ]
