PIC18F4580-I/PT 参数 Datasheet PDF下载

型号：	PIC18F4580-I/PT
PDF下载：	下载PDF文件查看货源
内容描述：	28 /40/ 44引脚增强型闪存微控制器与ECAN技术， 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用：	闪存微控制器和处理器外围集成电路时钟
文件页数/大小：	490 页 / 8912 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18F2480/2580/4480/4580

TABLE 5-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

Power-on Reset,

Brown-out Reset

WDT Reset,

RESETInstruction,

Stack Resets

Wake-up via WDT

or Interrupt

Applicable Devices

PIR2

PIE2

IPR1

PIR1

PIE1

2480 2580 4480 4580

00-0 0000

0--0 000-

00-0 0000

0--0 000-

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

--00 0000

0000 -111

1111 1111

1111 1111⁽⁵⁾

---- -xxx

xxxx xxxx

xxxx xxxx⁽⁵⁾

---- x000

xxxx xxxx

xx0x 0000⁽⁵⁾

0001 0000

0000 0000

--00 ----

00-0 0000

0--0 000-

00-0 0000

0--0 000-

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

--00 0000

0000 -111

1111 1111

1111 1111⁽⁵⁾

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- x000

uuuu uuuu

uu0u 0000⁽⁵⁾

0001 0000

0000 0000

--00 ----

uu-u uuuu⁽¹⁾

u--u uuu-⁽¹⁾

uu-u uuuu

u--u uuu-

uuuu uuuu

-uuu uuuu

uuuu uuuu⁽¹⁾

-uuu uuuu

uuuu uuuu

-uuu uuuu

--uu uuuu

uuuu -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- uuuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

uuuu uuuu

--uu ----

OSCTUNE

TRISE

TRISD

TRISC

TRISB

TRISA⁽⁵⁾

LATE

LATD

LATC

LATB

LATA⁽⁵⁾

PORTE

PORTD

PORTC

PORTB

PORTA⁽⁵⁾

ECANCON

TXERRCNT

RXERRCNT

COMSTAT

CIOCON

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 5-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

DS39637D-page 58

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