PIC18F2480/2580/4480/4580
Reset situations, as indicated in Table 5-3. These bits
are used in software to determine the nature of the
Reset.
5.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 5-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
TABLE 5-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
SBOREN
RI
TO
PD POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
u(2)
u(2)
u(2)
MCLR Reset during
Power-Managed Run modes
MCLR Reset during
Power-Managed Idle modes and
Sleep mode
0000h
u(2)
u
1
0
u
u
u
u
WDT Time-out during Full Power
or Power-Managed Run modes
0000h
0000h
u(2)
u(2)
u
u
0
u
u
u
u
u
u
u
u
u
u
u
MCLR Reset during Full-Power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u(2)
u(2)
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u(2)
u(2)
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT Time-out during
Power-Managed Idle or Sleep
modes
PC + 2
Interrupt Exit from
PC + 2
u(2)
u
u
0
u
u
u
u
Power-Managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01and SBOREN = 1); otherwise, the Reset state is ‘0’.
DS39637D-page 54
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
