PIC18F2480/2580/4480/4580
FIGURE 1-2:
Table Pointer<21>
inc/dec logic
21
20
8
PCLATU PCLATH
PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Data Latch
Data Memory
(.7, 1.5 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
inc/dec
logic
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
4
Access
Bank
12
PORTA
RA0/AN0/CV
REF
RA1/AN1
RA2/AN2/V
REF
-
RA3/AN3/V
REF
+
RA4/T0CKI
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
8
PCU PCH PCL
Program Counter
31 Level Stack
PORTB
RB0/INT0/FLT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
8
STKPTR
Table Latch
Instruction Bus <16>
ROM Latch
Address
Decode
IR
Instruction
Decode &
Control
State Machine
Control Signals
8
PRODH PRODL
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
PORTD
RD0/PSP0 /C1IN+
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
OSC1
(2)
OSC2
(2)
T1OSI
T1OSO
MCLR
(1)
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
8
ALU<8>
8
PORTE
Band Gap
Reference
V
DD
, V
SS
RE0/RD/AN5
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/V
PP
/RE3
(1)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
ECCP1
MSSP
EUSART
ADC
10-Bit
ECAN
Note
1:
2:
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to
for additional information.
©
2009 Microchip Technology Inc.
DS39637D-page 13
MICROCHIP [ MICROCHIP TECHNOLOGY ]
