PIC18F2480/2580/4480/4580
FIGURE 1-2:
PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Data Latch
8
8
inc/dec logic
21
Data Memory
(.7, 1.5 Kbytes)
PCLATU PCLATH
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
STKPTR
RB0/INT0/FLT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
4
Address Latch
Access
Bank
FSR0
FSR1
FSR2
Program Memory
(16/32 Kbytes)
12
Data Latch
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
IR
RC0/T1OSO/T13CKI
RC1/T1OSI
Instruction Bus <16>
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
State Machine
Control Signals
Instruction
Decode &
Control
PRODH PRODL
8 x 8 Multiply
3
PORTD
8
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
BITOP
8
W
8
8
Internal
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
Oscillator
Block
8
8
RD6/PSP6/P1C
RD7/PSP7/P1D
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
8 MHz
Oscillator
Watchdog
Timer
T1OSO
PORTE
RE0/RD/AN5
Band Gap
Reference
Brown-out
Reset
Fail-Safe
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/VPP/RE3(1)
MCLR(1)
VDD, VSS
Single-Supply
Programming
In-Circuit
Clock Monitor
Debugger
Data
EEPROM
BOR
HLVD
Timer0
ECCP1
Timer1
MSSP
Timer2
Timer3
ADC
10-Bit
Comparator
CCP1
EUSART
ECAN
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 3.0 “Oscillator Configurations” for additional information.
© 2009 Microchip Technology Inc.
DS39637D-page 13
MICROCHIP [ MICROCHIP ]
