PIC18F2480/2580/4480/4580
FIGURE 1-1:
PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
PORTA
8
8
inc/dec logic
21
RA0/AN0
RA1/AN1
Data Memory
(.7, 1.5 Kbytes)
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(16/32 Kbytes)
12
Data Latch
PORTB
RB0/INT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
inc/dec
logic
8
Table Latch
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address
Decode
ROM Latch
IR
Instruction Bus <16>
8
State Machine
Control Signals
Instruction
Decode &
Control
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI
3
8
RC2/CCP1
BITOP
8
W
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
8
Internal
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
RC6/TX/CK
RC7/RX/DT
Oscillator
Block
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
8 MHz
Oscillator
Watchdog
Timer
T1OSO
Band Gap
Reference
Brown-out
Reset
Fail-Safe
MCLR(1)
VDD, VSS
Single-Supply
Programming
In-Circuit
PORTE
Clock Monitor
MCLR/VPP/RE3(1)
Debugger
Data
EEPROM
BOR
HLVD
Timer0
ECCP1
Timer1
MSSP
Timer2
Timer3
ADC
10-Bit
Comparator
CCP1
EUSART
ECAN
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 3.0 “Oscillator Configurations” for additional information.
DS39637D-page 12
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
