PIC18F2420/2520/4420/4520
19.8
Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
ACQ
time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2:
Name
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
(4)
TRISE
(4)
LATE
(4)
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7
Bit 6
Bit 5
TMR0IE
RCIF
RCIE
RCIP
—
—
—
Bit 4
INT0IE
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 3
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
Bit 2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
Bit 1
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
Reset
Values
on page
CHS2
VCFG0
ACQT1
RA4
RB4
CHS1
PCFG3
ACQT0
RA3
RB3
CHS0
PCFG2
ADCS2
RA2
RB2
GO/DONE
PCFG1
ADCS1
RA1
RB1
ADON
PCFG0
ADCS0
RA0
RB0
RE2
TRISE2
RE1
TRISE1
RE0
TRISE0
—
PSPMODE
—
RE3
(3)
—
—
GIE/GIEH PEIE/GIEL
PSPIF
(1)
PSPIE
(1)
PSPIP
(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
ADFM
RA7
(2)
TRISA7
(2)
RB7
—
—
—
RA6
(2)
TRISA6
(2)
RB6
CHS3
VCFG1
ACQT2
RA5
RB5
PORTA Data Direction Register
PORTB Data Direction Register
PORTB Data Latch Register (Read and Write to Data Latch)
—
IBF
—
—
OBF
—
—
IBOV
—
PORTE Data Latch Register
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2:
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3:
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4:
These registers are not implemented on 28-pin devices.
DS39631E-page 232
©
2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
